Result: Effective automatic parallelization of stencil computations
Title:
Effective automatic parallelization of stencil computations
Authors:
Source:
PLDI'07 Proceedings of the 2007 ACM SIGPLAN Conference on Programming Language Design & Implementation, June 10-13, 2007, San Diego, CAACM SIGPLAN notices. 42(6):235-244
Publisher Information:
Broadway, NY: ACM, 2007.
Publication Year:
2007
Physical Description:
print, 29 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Langages de programmation, Programming languages, Organisation des mémoires. Traitement des données, Memory organisation. Data processing, Gestion des mémoires et des fichiers (y compris la protection et la sécurité des fichiers), Memory and file management (including protection and security), Accès mémoire, Storage access, Acceso memoria, Algorithme parallèle, Parallel algorithm, Algoritmo paralelo, Code temps, Time code, Código tiempo, Compilateur, Compiler, Compilador, Equilibrage charge, Load balancing, Equilibrio de carga, Haute performance, High performance, Alto rendimiento, Langage programmation, Programming language, Lenguaje programación, Optimisation programme, Program optimization, Optimización programa, Parallélisme, Parallelism, Paralelismo, Pavage, Tiling, Processeur pipeline, Pipeline processor, Procesador oleoducto, Surcharge, Overload, Sobrecarga, Parallélisation automatique, Automatic parallelization, Paralelización automática, Algorithms, Load balance, Performance, Stencil computations
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Dept. of Computer Science and Engineering The Ohio State University 2015 Neil Ave, Columbus, OH, United States
Dept. of Electrical & Computer Engg. and Center for Computation & Technology Louisiana State University, United States
Dept. of Electrical & Computer Engg. and Center for Computation & Technology Louisiana State University, United States
ISSN:
1523-2867
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Accession Number:
edscal.19110789
Database:
PASCAL Archive
Further Information
Performance optimization of stencil computations has been widely studied in the literature, since they occur in many computationally intensive scientific and engineering applications. Compiler frameworks have also been developed that can transform sequential stencil codes for optimization of data locality and parallelism. However, loop skewing is typically required in order to tile stencil codes along the time dimension, resulting in load imbalance in pipelined parallel execution of the tiles. In this paper, we develop an approach for automatic parallelization of stencil codes, that explicitly addresses the issue of load-balanced execution of tiles. Experimental results are provided that demonstrate the effectiveness of the approach.