• Enhancing last-level cache per...

Result: Enhancing last-level cache performance by block bypassing and early miss determination

Title:
Enhancing last-level cache performance by block bypassing and early miss determination
Authors:
DYBDAHL, Haakon, STENSTRÖM, Per
Source:
Advances in computer systems architecture (11th Asia-Pacific conference, ACSAC 2006, Shanghai, China, September 6-8, 2006)Lecture notes in computer science. :52-66
Publisher Information:
Berlin: Springer, 2006.
Publication Year:
2006
Physical Description:
print, 16 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Matériel informatique, Hardware, Ordinateurs, microordinateurs, Computers, microcomputers, Antémémoire, Cache memory, Antememoria, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Complexité algorithme, Algorithm complexity, Complejidad algoritmo, Dérivation, Bypass, Derivación, Gestion mémoire, Storage management, Gestión memoria, Hiérarchie mémoire, Memory hierarchy, Jerarquía memoria, Pipeline, Oleoducto, Processeur pipeline, Pipeline processor, Procesador oleoducto, Réutilisation, Reuse, Reutilización
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Dept. of Computer and Information Science,Norwegian University of Science and Technology, 7491 Trondheim, Norway
Dept. of Computer Engineering, Dept. of Computer Engineering, Chalmers University of Technology, 412 96 Goteborg, Sweden
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19161748
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.19161748
Database:
PASCAL Archive

Further Information

While bypassing algorithms have been applied to the first-level cache, we study for the first time their effectiveness for the last-level caches for which miss penalties are significantly higher and where algorithm complexity is not constrained by the speed of the pipeline. Our algorithm monitors the reuse behavior of blocks that are touched by delinquent loads and re-classify them on-the-fly. Blocks classified as bypassed are only installed in the level-1 cache. We leverage the algorithm to early send out a miss request for loads expected to request blocks classified to be bypassed. Such requests are sent to memory directly without tag checks at intermediary levels in the cache hierarchy. Overall, we find that we can robustly reduce the miss rate by 23% and improve IPC with 14% on average for memory bound SPEC2000 applications without degrading performance of the other SPEC2000 applications.