• The algorithm and circuit desi...

Result: The algorithm and circuit design of a 400MHz 16-bit hybrid multiplier

Title:
The algorithm and circuit design of a 400MHz 16-bit hybrid multiplier
Authors:
LI ZHENTAO, CHEN SHUMING, LI ZHAOLIANG, LEI CONGHUA
Source:
Advances in computer systems architecture (11th Asia-Pacific conference, ACSAC 2006, Shanghai, China, September 6-8, 2006)Lecture notes in computer science. :401-408
Publisher Information:
Berlin: Springer, 2006.
Publication Year:
2006
Physical Description:
print, 9 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Matériel informatique, Hardware, Ordinateurs, microordinateurs, Computers, microcomputers, Additionneur, Adder, Adicionador, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Calcul réparti, Distributed computing, Cálculo repartido, Calculateur SIMD, SIMD computer, Conception circuit, Circuit design, Diseño circuito, Haute performance, High performance, Alto rendimiento, Mode propre, Eigenmode, Modo propio, Multiplicateur, Multiplier, Multiplicador, Multiplication, Multiplicación, Méthode arborescente, Tree structured method, Método arborescente, Parallélisme, Parallelism, Paralelismo, Point fixe, Fix point, Punto fijo, Processeur 16 bits, 16 bit Processor, Procesador 16 bits, Sous produit, By product, Subproducto, Structure arborescente, Tree structure, Estructura arborescente, Système aide décision, Decision support system, Sistema ayuda decisíon, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Théorème point fixe, Fixed point theorem, Teorema punto fijo
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
School of Computer Science and Technology, National University of Defense Technology, 410073 Changsha, China
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19161778
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.19161778
Database:
PASCAL Archive

Further Information

In this paper we present the algorithm of a 16-bit hybrid multiplier, which can work in two modes. In normal mode, it performs a 16-bit multiplication. In SIMD mode, it performs two parallel 8-bit multiplications. The proposed algorithm is based on the raix-4 modified Booth's algorithm. Our algorithm generates ten partial products and a modifier, which is five less than the other algorithms. We can get one 32-bit product or two 16-bit products by directly accumulating the ten partial products and the modifier, easing the design of the tree structures for compressing the partial products and the final adder. The proposed algorithm is adopted by YHFT-DSP/800, a high performance fixed-point DSP. The multiplier was full custom designed in 0.1 Sum CMOS technology. We also designed a test chip. The test results show the multiplier works well at 400MHz in normal mode, 480MHz in SIMD mode. The simulated power is 35.8 mW at 400MHz, and 42.5 mW at 480MHz.