Treffer: The new BCD subtractor and its reversible logic implementation
Title:
The new BCD subtractor and its reversible logic implementation
Authors:
Source:
Advances in computer systems architecture (11th Asia-Pacific conference, ACSAC 2006, Shanghai, China, September 6-8, 2006)Lecture notes in computer science. :466-472
Publisher Information:
Berlin: Springer, 2006.
Publication Year:
2006
Physical Description:
print, 10 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Informatique théorique, Theoretical computing, Algorithmique. Calculabilité. Arithmétique ordinateur, Algorithmics. Computability. Computer arithmetics, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Matériel informatique, Hardware, Ordinateurs, microordinateurs, Computers, microcomputers, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Calcul optique, Optical computing, Cálculo óptico, Calcul quantique, Quantum computation, Calculo cuántico, Commande optimale, Optimal control, Control óptimo, Conception optimale, Optimal design, Concepción optimal, Logique quantique, Quantum logic, Lógica cuántica, Nanotechnologie, Nanotechnology, Nanotecnología, Optimisation, Optimization, Optimización, Porte logique, Logic gate, Puerta lógica, Puissance faible, Low power, Potencia débil, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Virgule flottante, Floating point, Coma flotante
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Center for VLSI and Embedded System Technologies International Institute of Information Technology, Hyderabad-500032, India
ISSN:
0302-9743
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.19161787
Database:
PASCAL Archive
Weitere Informationen
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Thus in this paper we propose a novel BCD subtractor called carry skip BCD subtractor. We also propose the reversible logic implementation of the proposed carry skip BCD subtractor. Reversible logic is emerging as a promising computing paradigm having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. It is being tried to design the BCD subtractor optimal in terms of number of reversible gates and garbage outputs.