Result: A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video

Title:
A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video
Authors:
KUO, Huang-Chih, WU, Li-Cian, HUANG, Hao-Ting, HSU, Sheng-Tsung, LIN, Youn-Long
Source:
IEEE transactions on very large scale integration (VLSI) systems. 19(6):925-938
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2011.
Publication Year:
2011
Physical Description:
print, 15 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Convertisseurs de signal, Signal convertors, Circuit intégré, Integrated circuit, Circuito integrado, Architecture circuit, Circuit architecture, Arquitectura circuito, Circuit VLSI, VLSI circuit, Circuito VLSI, Circuit codeur, Coding circuit, Circuito codificación, Codage adaptatif, Adaptive coding, Codificación adaptativa, Codage binaire, Binary coding, Codificación binaria, Code arithmétique, Arithmetic code, Código aritmético, Consommation électricité, Electric power consumption, Consumo electricidad, Electronique faible puissance, Low-power electronics, Etat actuel, State of the art, Estado actual, Evaluation performance, Performance evaluation, Evaluación prestación, Haute performance, High performance, Alto rendimiento, Horloge, Clock, Reloj, Logiciel, Software, Logicial, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, H.264/AVC, VLSI architecture, intra-frame encoder
Document Type:
Academic journal Article
File Description:
text
Language:
English
Author Affiliations:
Department of Computer Science, National Tsing Hua University, HsinChu 300, Tawain, Province of China
ISSN:
1063-8210
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=24220425
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.24220425
Database:
PASCAL Archive

Further Information

H.264/AVC intra-frame encoding contains several computation-intensive coding tools that form a long data dependency loop that is difficult to speed up. In this paper, we present a low-power and high-performance H.264/AVC intra-frame encoder. We propose several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4 × 4 luma blocks, integrate an efficient CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized into a TSMC 0.13 μm CMOS cell library, our design requires 265.3 K gates at 114 MHz and consumes 23.56 mW to encode 1080pHD (1920 × 1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. Compared with all state-of-the-art designs, our design has a lower working frequency and achieves both better bit-rate saving and lower power consumption.