• Low-power context-based adapti...

Treffer: Low-power context-based adaptive binary arithmetic encoder using an embedded cache

Title:
Low-power context-based adaptive binary arithmetic encoder using an embedded cache
Authors:
LEI, S.-F, LO, C.-C, KUO, C.-C, SHIEH, M.-D
Source:
IET image processing (Print). 6(4):309-317
Publisher Information:
Stevenage: Institution of Engineering and Technology, 2012.
Publication Year:
2012
Physical Description:
print, 22 ref
Original Material:
INIST-CNRS
Subject Terms:
Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Telecommunications et theorie de l'information, Telecommunications and information theory, Théorie de l'information, du signal et des communications, Information, signal and communications theory, Théorie du signal et des communications, Signal and communications theory, Codage, codes, Coding, codes, Traitement du signal, Signal processing, Traitement des images, Image processing, Circuit codeur, Coding circuit, Circuito codificación, Codage adaptatif, Adaptive coding, Codificación adaptativa, Codage binaire, Binary coding, Codificación binaria, Codage vidéo, Video coding, Code arithmétique, Arithmetic code, Código aritmético, Code bloc, Block code, Código bloque, Complexité calcul, Computational complexity, Complejidad computación, Consommation électricité, Electric power consumption, Consumo electricidad, Débit information, Information rate, Índice información, Electronique faible puissance, Low-power electronics, Implémentation, Implementation, Implementación, Mappage, Mapping, Carta de datos, Méthode statistique, Statistical method, Método estadístico, Taux compression, Compression ratio, Relación compresión, Traitement signal vidéo, Video signal processing, Transmission donnée, Data transmission, Transmisión datos, Transmission information, Information transmission, Transmisión información
Document Type:
Fachzeitschrift Article
File Description:
text
Language:
English
Author Affiliations:
Department of Electrical Engineering, National Cheng Kung University, Tawain, Province of China
ISSN:
1751-9659
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=26007185
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Telecommunications and information theory
Accession Number:
edscal.26007185
Database:
PASCAL Archive

Weitere Informationen

H.264/AVC achieves a higher compression ratio than previous standards. However, this standard is also more complex because of the use of methods such as context-based adaptive binary arithmetic coding (CABAC). The high computational complexity of CABAC results in large power consumption. This study presents a systematic analysis for designing a low-power architecture which includes an embedded cache. The analysis provides the mapping scheme between the cache and the main memory where the contexts are stored. The observations for the proposed scheme are based on the statistical correlation between neighbouring blocks for H.264 coding. The proposed scheme allows the context access operations to hit frequently in the cache, significantly reducing the power consumption. The proposed architecture lowers power consumption by up to 50% compared to designs without embedded cache. An efficient bit-packing method of output bitstream that can be implemented by pipeline structure for high encoding data throughput is also proposed. The throughput of the proposed design is up to 200 Mbins per second for H.264 main profile.