Treffer: Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement

Title:
Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement
Authors:
OUNI, Bouraoui, MTIBAA, Abdellatif
Source:
Microelectronics international. 29(2):101-107
Publisher Information:
Bradford: MCB University Press, 2012.
Publication Year:
2012
Physical Description:
print, 1/4 p
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Algorithme, Algorithm, Algoritmo, Architecture reconfigurable, Reconfigurable architectures, Circuit intégré, Integrated circuit, Circuito integrado, Conception optimale, Optimal design, Concepción optimal, Module multipuce, Multichip module, Modulo multipulga, Positionnement, Positioning, Posicionamiento, Réseau porte programmable, Field programmable gate array, Red puerta programable, Théorie algorithme, Algorithm theory, Valeur propre, Eigenvalue, Valor propio, Is Integrated circuits, Micro-circuit technology, Multi chip modules, Programming and algorithm theory
Document Type:
Fachzeitschrift Article
File Description:
text
Language:
English
Author Affiliations:
Faculte des Science de Monastir, Ecole Nationales d'Ingenieurs de Sousse, Monstir, Tunisia
ISSN:
1356-5362
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=26020336
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.26020336
Database:
PASCAL Archive

Weitere Informationen

Purpose ― The purpose of this paper is to reduce the reconfiguration time of a field-programmable gate array (FPGA). Design/methodology/approach ― The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time. Findings - Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms. Originality/value - The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well-known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.