• Reducing random-dopant fluctua...

Treffer: Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Title:
Reducing random-dopant fluctuation impact using footer transistors in many-core systems
Authors:
MAJZOUB, Sohaib
Source:
Integration (Amsterdam). 48:46-54
Publisher Information:
Amsterdam: Elsevier, 2015.
Publication Year:
2015
Physical Description:
print, 38 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Basse tension, Low voltage, Baja tensión, Circuit logique, Logic circuit, Circuito lógico, Ecart type, Standard deviation, Desviación típica, Economies d'énergie, Energy savings, Ahorros energía, Evaluation performance, Performance evaluation, Evaluación prestación, Impureté, Impurity, Impureza, Logique seuil, Threshold logic, Lógica umbral, Modélisation, Modeling, Modelización, Nanotechnologie, Nanotechnology, Nanotecnología, Porte logique, Logic gate, Puerta lógica, Processus stochastique, Stochastic process, Proceso estocástico, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Seuil tension, Voltage threshold, Umbral tensión, Temps retard, Delay time, Tiempo retardo, Transistor MOS complémentaire, Complementary MOS transistor, Transistor MOS complementario, Valeur moyenne, Mean value, Valor medio, Core speed variation, Footer transistor, Many-core, Multi-Vdd design, Multi-Vt design, Multi-core, Process variation, Process voltage and temperature variations, Random dopant fluctuation, Simulation, System level modeling, Voltage scaling
Document Type:
Fachzeitschrift Article
File Description:
text
Language:
English
Author Affiliations:
Department of Electrical Engineering, King Saud University, P.O. Box 800, Riyadh 11421, Saudi Arabia
ISSN:
0167-9260
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=28891130
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.28891130
Database:
PASCAL Archive

Weitere Informationen

Process variation creates core-speed discrepancy among the core in a many-core platforms. Random variation is one of the important components that contributes into core-speed discrepancy. In this paper, we propose a novel technique that uses footer transistors to reduce the impact of random process variation on delay and power in a many-core platform. Process variation is due to many fundamental deficiencies, impurities, and imperfections during the fabrication process at the nano-scale technologies. The results of this variation have a direct impact on two key parameters of the CMOS transistor: threshold voltage and gate length, which have major implication on the core speed and power. The random component of this variation is mostly attributed to the random-dopant fluctuation, which results in threshold voltage discrepancy among the cores. The proposed technique reduces the random dopant fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor. The results show a reduction of the total standard deviation from 25% down to 17% using the proposed method. Furthermore, the average energy saving of 30 different applications mapped on a many-core platform is improved by around 5%, and the performance by around 6%. .