Treffer: A synchronous latency-insensitive RISC for better than worst-case design

Title:
A synchronous latency-insensitive RISC for better than worst-case design
Authors:
CASU, Mario R, MANTOVANI, Paolo
Source:
Integration (Amsterdam). 48:72-82
Publisher Information:
Amsterdam: Elsevier, 2015.
Publication Year:
2015
Physical Description:
print, 41 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Autotest, Built in self test, Autoprueba, Chemin critique, Critical path, Recorrido crítico, Circuit intégré CMOS, CMOS integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Evaluation performance, Performance evaluation, Evaluación prestación, Horloge, Clock, Reloj, Logiciel, Software, Logicial, Méthode cas pire, Worst case method, Método caso peor, Processeur RISC, RISC processor, Procesador RISC, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Temps retard, Delay time, Tiempo retardo, Better than worst-case (BTWC) design, Latency-insensitive design, Variable-latency
Document Type:
Fachzeitschrift Article
File Description:
text
Language:
English
Author Affiliations:
Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino, Italy
Department of Computer Science, Columbia University, New York, NY, United States
ISSN:
0167-9260
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=28891132
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.28891132
Database:
PASCAL Archive

Weitere Informationen

Variability of process parameters in nanometer CMOS circuits makes standard worst-case design methodology waste much of the advantages of scaling. A common-case design, though, is a perilous alternative, as it gives up much of the design yield. Better than worst-case (BTWC) design methodology reconciles performance and yield. In this paper we present a BTWC RISC processor that tolerates worst-case extra delays of critical paths without significant impact on the overall performance. We obtain this result by coupling latency-insensitive design and variable-latency (VL) units. A software built-in self-test checks VL units individually to determine whether to activate them or not. Compared to a worst-case approach, the RISC clock frequency increases by 23% in a 45 nm CMOS technology. The impact of VL on instructions per cycle is circumscribed to the worst process case only and very limited, as we show through a set of benchmarks.