Result: Stochastic logical effort as a variation aware delay model to estimate timing yield

Title:
Stochastic logical effort as a variation aware delay model to estimate timing yield
Authors:
BAYRAKCI, Alp Arslan
Source:
Integration (Amsterdam). 48:101-108
Publisher Information:
Amsterdam: Elsevier, 2015.
Publication Year:
2015
Physical Description:
print, 17 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Diminution coût, Cost lowering, Reducción costes, Estimateur, Estimator, Estimador, Estimation paramètre, Parameter estimation, Estimación parámetro, Matrice formage, Die, Matriz formadora, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Méthode statistique, Statistical method, Método estadístico, Simulation numérique, Numerical simulation, Simulación numérica, Système intelligent, Intelligent system, Sistema inteligente, Temps retard, Delay time, Tiempo retardo, Transistor, Logical effort, Monte Carlo, Statistical timing analysis, Timing yield estimation
Document Type:
Academic journal Article
File Description:
text
Language:
English
Author Affiliations:
Department of Computer Engineering, Gebze Institute of Technology, Turkey
ISSN:
0167-9260
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=28891134
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.28891134
Database:
PASCAL Archive

Further Information

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180 x on the average for ISCAS'85 benchmark circuits and in the existence of both inter- and intra-die variations.