Treffer: An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids

Title:
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids
Source:
Integration (Amsterdam). 48:230-238
Publisher Information:
Amsterdam: Elsevier, 2015.
Publication Year:
2015
Physical Description:
print, 29 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Filtres de fréquence, Frequency filters, Circuits numériques, Digital circuits, Banc filtre, Filter bank, Banco filtro, Circuit additionneur, Summing circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit multiplicateur, Multiplying circuits, Conception compacte, Compact design, Concepción compacta, Consommation électricité, Electric power consumption, Consumo electricidad, Correction optique de proximité, Optical proximity correction, Corrección de proximidad óptica, Electronique faible puissance, Low-power electronics, Energie minimale, Minimum energy, Energía mínima, Evaluation performance, Performance evaluation, Evaluación prestación, Filtre numérique, Digital filter, Filtro numérico, Filtre retard, Delay filters, Filtre réponse impulsion finie, Finite impulse response filter, Filtro respuesta impulsión acabada, Implémentation, Implementation, Implementación, Montage cascade, Cascade connection, Conexión cascada, Parallélisme, Parallelism, Paralelismo, Phase linéaire, Linear phase, Fase lineal, Processeur 16 bits, 16 bit Processor, Procesador 16 bits, Précision élevée, High precision, Precisión elevada, Rapport signal bruit, Signal to noise ratio, Relación señal ruido, Silicium, Silicon, Silicio, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Virgule flottante, Floating point, Coma flotante, ANSI S1.11 1/3-octave filter bank, Cascaded datapath, Hearing aid, Linear-phase FIR filter, Static floating-point arithmetic
Document Type:
Fachzeitschrift Article
File Description:
text
Language:
English
Author Affiliations:
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Tawain, Province of China
ISSN:
0167-9260
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.28891146
Database:
PASCAL Archive

Weitere Informationen

The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital hearing aids. In the proposed SFP LPFIR (linear-phase finite impulse response) filter engine, lower silicon area and lesser power consumption facilitate better SNR performance than that achieved with the conventional post-truncation (PT) datapath with integer arithmetic. Moreover, in the proposed LPFIR filter engine, a cascaded 16-bit SFP A-M-S-Acc datapath is used that consists of two embedded 1-bit shifters to improve hardware usage and parallelism, one 16-bit DT adder (A), one 16-bit DT multiplier (M), one 16-bit barrel shifter (S), and one 16-bit DT accumulator (Acc). The operations per cycle (OPC) of the proposed SFP LPFIR filter engine reaches 6, which enables efficient fabrication of the low-latency AFB for hearing aids. To verify the effectiveness of the proposed 16-bit SFP LPFIR filter engine, a 10-ms 18-band quasi-ANSI S1.11 1/3-octave AFB for digital hearing aids was implemented using UMC 90-nm CMOS technology. The AFB was operated at 792 kHz to process, in real-time, 24 kHz audio, with the power consumption being approximately 80.6 μW (at 1 V). Compared to the previous design in which the conventional PT datapath with integer arithmetic was used, approximately 9.6% of total power and 8.3% of silicon area were saved and almost the same SNR (signal-to-noise ratio) performance was achieved with the new system, when evaluated by a 3.96-s sequence of Mandarin speech.