Treffer: Reconfiguring processor arrays using multiple-track models : the 3-track-1-square-approach
Title:
Reconfiguring processor arrays using multiple-track models : the 3-track-1-square-approach
Authors:
Source:
IEEE transactions on computers. 42(11):1281-1293
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 1993.
Publication Year:
1993
Physical Description:
print, 17 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Matériel informatique, Hardware, Informatique répartie, Distributed computer systems, Parallélisme, Parallelism, Paralelismo, Tolérance faute, Fault tolerance, Tolerancia falta, Algorithme efficace reconfiguration temps polynomial, Efficient polynomial-time reconfiguration algorithm, Tableau processeur, Processor array
Document Type:
Fachzeitschrift
Article
File Description:
text
Language:
English
Author Affiliations:
AT&T Bell Laboratories, Holmdel NJ 07733, United States
ISSN:
0018-9340
Rights:
Copyright 1994 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.3886398
Database:
PASCAL Archive
Weitere Informationen
We present new results on systematic procedures for reconfiguring processor arrays in the presence of faulty processors. In particular, we consider models that use multiple tracks along every channel and a single spare row (or column) of processing elements (PE's) along each boundary of the array. In the presence of faulty PE's the general methodology for reconfiguration involves replacing every faulty PE logically (rather than physically) by a spare PE through a sequence of logical substitutions; these sequences of substitutions are referred to as compensation palhs. The determination of such compensation paths for every faulty PE has to be followed by an algorithm to connect each PE to its logical neighbors.