American Psychological Association 6th edition

LOURENCO, N., CANELAS, A., POVOA, R., MARTINS, R., & HORTA, N. (2015). Floorplan-aware analog IC sizing and optimization based on topological constraints. Integration (Amsterdam), 48, 183-197.

ISO-690 (author-date, English)

LOURENCO, Nuno, CANELAS, António, POVOA, Ricardo, MARTINS, Ricardo und HORTA, Nuno, 2015. Floorplan-aware analog IC sizing and optimization based on topological constraints. Integration (Amsterdam). 1 Januar 2015. Vol. 48, , p. 183-197.

Modern Language Association 9th edition

LOURENCO, N., A. CANELAS, R. POVOA, R. MARTINS, und N. HORTA. „Floorplan-Aware Analog IC Sizing and Optimization Based on Topological Constraints“. Integration (Amsterdam), Bd. 48, Januar 2015, S. 183-97.

Mohr Siebeck - Recht (Deutsch - Österreich)

LOURENCO, Nuno/CANELAS, António/POVOA, Ricardo/MARTINS, Ricardo/HORTA, Nuno: Floorplan-aware analog IC sizing and optimization based on topological constraints, Integration (Amsterdam) 2015, 183-197.

Emerald - Harvard

LOURENCO, N., CANELAS, A., POVOA, R., MARTINS, R. und HORTA, N. (2015), „Floorplan-aware analog IC sizing and optimization based on topological constraints“, Integration (Amsterdam), Vol. 48, S. 183-197.

Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.