• Design and FPGA implementation...

Result: Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations

Title:
Design and FPGA implementation of an efficient parallel Turbo decoder for combining state metric calculations
Authors:
Qian ZHANG, Ming ZHAN, Jianwu ZHANG, Fulong WANG, Yunkai1 FENG, Hao TANG
Source:
Dianxin kexue, Vol 38, Pp 47-58 (2022)
Publisher Information:
Beijing Xintong Media Co., Ltd, 2022.
Publication Year:
2022
Collection:
LCC:Telecommunication
LCC:Technology
Subject Terms:
state measure merge calculation, Turbo code, FPGA implementation, parallel algorithm, Telecommunication, TK5101-6720, Technology
Document Type:
Academic journal article
File Description:
electronic resource
Language:
Chinese
ISSN:
1000-0801
Relation:
https://doaj.org/toc/1000-0801
DOI:
10.11959/j.issn.1000-0801.2022023
Access URL:
https://doaj.org/article/2fdf554f48c74b6a9e368b77d70ca0a6
Accession Number:
edsdoj.2fdf554f48c74b6a9e368b77d70ca0a6
Database:
Directory of Open Access Journals

Further Information

In order to achieve the requirement of high throughput and low-power in wireless communication, a parallel Turbo decoder has attracted extensive attention.By analyzing the calculating of the state metrics, a low-resource parallel Turbo decoder architecture scheme based on merging the forward and backward state metrics calculation modules was proposed, and effectiveness of the new architecture was demonstrated through field-programmable gate array (FPGA) hardware realization.The results show that, compared with the existing parallel Turbo decoder architectures, the proposed design architecture reduces the logic resource of state metrics calculation module about 50%, while the dynamic power dissipation of the decoder architecture is decreased by 5.26% at the frequency of 125 MHz.Meanwhile the decoding algorithm is close to the decoding performance of the parallel algorithm.