Result: Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach

Title:
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach
Authors:
Schoeberl, Martin, Schleuniger, Pascal, Puffitsch, Wolfgang, Brandner, Florian, Probst, Christian W., Karlsson, Sven, Thorn, Tommy
Contributors:
Department of Informatics and Mathematical Modeling [Lyngby] (DTU), Danmarks Tekniske Universitet = Technical University of Denmark (DTU), Institute of Computer Engineering [Vienna], Vienna University of Technology = Technische Universität Wien (TU Wien), Compilation and embedded computing systems (COMPSYS), Centre Inria de l'Université Grenoble Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire de l'Informatique du Parallélisme (LIP), École normale supérieure de Lyon (ENS de Lyon), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure de Lyon (ENS de Lyon), Université de Lyon-Centre National de la Recherche Scientifique (CNRS), Unaffiliated Researcher, Philipp Lucas, Lothar Thiele, Benoit Triquet, Theo Ungerer, and Reinhard Wilhelm, Philipp Lucas and Lothar Thiele and Benoit Triquet and Theo Ungerer and Reinhard Wilhelm
Source:
Bringing Theory to Practice: Predictability and Performance in Embedded Systems. :11-21
Publisher Information:
CCSD, 2011.
Publication Year:
2011
Collection:
collection:ENS-LYON
collection:CNRS
collection:INRIA
collection:UNIV-LYON1
collection:INRIA-RHA
collection:LIP
collection:INRIA_TEST
collection:TESTALAIN1
collection:INRIA2
collection:INRIA-RENGRE
collection:UDL
collection:UNIV-LYON
collection:INRIA-ETATSUNIS
Subject Terms:
WCET-aware Compilation, WCET Analysis, Time-predictable Architecture, ACM: C.: Computer Systems Organization, C.3: SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS, C.3.2: Real-time and embedded systems, C.1: PROCESSOR ARCHITECTURES, C.1.1: Single Data Stream Architectures, C.1.1.2: RISC, CISC, VLIW architectures, [INFO.INFO-AR]Computer Science [cs], Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs], Embedded Systems, [INFO.INFO-PF]Computer Science [cs], Performance [cs.PF]
Subject Geographic:
Grenoble, France
Original Identifier:
HAL:
Document Type:
Conference conferenceObject<br />Conference papers
Language:
English
Relation:
info:eu-repo/semantics/altIdentifier/doi/10.4230/OASIcs.PPES.2011.11
DOI:
10.4230/OASIcs.PPES.2011.11
Access URL:
https://inria.hal.science/inria-00585320
https://inria.hal.science/inria-00585320v1/document
https://inria.hal.science/inria-00585320v1/file/schoeberl-ppes11.pdf
Rights:
info:eu-repo/semantics/OpenAccess
Accession Number:
edshal.inria.00585320v1
Database:
HAL

Further Information

Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case performance are hard to be modeled for the WCET analysis. In this paper we present Patmos, a processor optimized for low WCET bounds rather than high average case performance. Patmos is a dual- issue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average case performance.