Result: VHDL simulation of the implementation of a costfunction circuit

Title:
VHDL simulation of the implementation of a costfunction circuit
Authors:
Lee, Chin-Hwa, Butler, Jon T., Naval Postgraduate School (U.S.), Electrical Engineering, Imvidhaya, Ming
Publisher Information:
Monterey, California: Naval Postgraduate School 1990-09 2013-08-01T21:15:44Z 2013-08-01T21:15:44Z 1990-09
Document Type:
Electronic Resource Electronic Resource
Index Terms:
VHDL (Computer hardware description language), Computer-aided design, Computer programs, Logic circuits, Integrated circuits, Computer-aided design., VHDL, costfunction, hardware description language, Thesis
URL:
https://hdl.handle.net/10945/34901
Availability:
Open access content. Open access content
Copyright is reserved by the copyright owner.
Note:
vi, 78 p. ill.
application/pdf
en_US
Other Numbers:
AD# oai:calhoun.nps.edu:10945/34901
1370304600
Contributing Source:
NAVAL POSTGRADUATE SCH
From OAIster®, provided by the OCLC Cooperative.
Accession Number:
edsoai.on1370304600
Database:
OAIster

Further Information

Since VHDL is a DoD standard hardware description language, it is widely used in the design of logic circuits at different levels. VHDL can be used to do behavioral modeling which is desirable in top-down system design. A cost function calculation in a graph partition algorithm is used here as an example to test the VHDL design methodology. Subroutines or statements in the software can be implemented into hardware if the subroutines or the statements in that software are suitably grouped. While the design of hardware is considered, high density integration of circuit is also the primary goal. Parts of an old design were condensed using programmable EPLDs which were programmed by commercial software development tools. The methodology of implementation goes from a register transfer language description to data flow design and control flow design. The costfunction calculation was successfully put into 4 EP1800 chips and the design was simulated in VHDL. The primary goal of integration was achieved at the expense of speed. To support the total simulation several behavior models were created. Results of simulation revealed that the adder circuit in the EP1800 can be further improved. Experiences of using VHDL are discussed in this thesis.
http://archive.org/details/vhdlsimulationof1094534901
Lieutenant Commander, Royal Thai Navy
Approved for public release; distribution is unlimited.
Approved for public release; distribution is unlimited.