Taşel, F. S., & Saran, A. N. (2025). Improved arithmetic efficiency in TFHE through gate-level optimizations. The Journal of Supercomputing: An International Journal of High-Performance Computer Design, Analysis, and Use, 81(18). https://doi.org/10.1007/s11227-025-08107-8

TAŞEL, Faris Serdar und SARAN, Ayşe Nurdan, 2025. Improved arithmetic efficiency in TFHE through gate-level optimizations. The Journal of Supercomputing: An International Journal of High-Performance Computer Design, Analysis, and Use. 1 Dezember 2025. Vol. 81, no. 18, . DOI 10.1007/s11227-025-08107-8.

Taşel, F. S., und A. N. Saran. „Improved Arithmetic Efficiency in TFHE through Gate-Level Optimizations“. The Journal of Supercomputing: An International Journal of High-Performance Computer Design, Analysis, and Use, Bd. 81, Nr. 18, Dezember 2025, https://doi.org/10.1007/s11227-025-08107-8.

Taşel, Faris Serdar/Saran, Ayşe Nurdan: Improved arithmetic efficiency in TFHE through gate-level optimizations, The Journal of Supercomputing: An International Journal of High-Performance Computer Design, Analysis, and Use 2025,

Taşel, F.S. und Saran, A.N. (2025), „Improved arithmetic efficiency in TFHE through gate-level optimizations“, The Journal of Supercomputing: An International Journal of High-Performance Computer Design, Analysis, and Use, Vol. 81 No. 18, verfügbar unter:https://doi.org/10.1007/s11227-025-08107-8.