Treffer: Analysis of fault tolerance capability of QCA circuit under regular clocking.

With significant progress in device scaling, current CMOS technology faces challenges such as low device density and increased power dissipation. Quantum-dot Cellular Automata (QCA) stands as one of the alternative nanotechnologies that proved viable to overcome these hurdles. The fundamental building block for implementing logic circuits is a QCA cell, which includes two vertically positioned electrons within four quantum dots. The majority gate and inverters are considered to be the fundamental primitives in QCA. On the other hand, clocking serves a crucial part in ensuring the correct synchronisation and information transmission within a circuit. Furthermore, regular clocking resolves fabrication pitfalls at the nanoscale and supports scalability. However, defects remain a concern in nanoscale circuit realisation. This research investigates the performance of logic circuits realised in regular clocking concerning the potentiality to tolerate faults. The circuits in both combinational and sequential logic are examined. For this purpose, the HDLQ and QCADesigner simulators are utilised. In accordance with the investigation, the performance of the circuits realised using zig–zag clocking is noteworthy, whereas the USE clock is noticed in a few cases. [ABSTRACT FROM AUTHOR]

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