Treffer: Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA.

Reversible logic has emerged as a transformative approach to energy-efficient computing by enabling reversible computations and minimizing information loss, thereby reducing energy dissipation to negligible levels. This innovation is particularly relevant in the era of low-power and sustainable system design. Among its applications, the Binary-Coded Decimal (BCD) adder, a cornerstone of digital arithmetic, plays a vital role in domains such as financial modeling, signal processing, and embedded systems. This study introduces a novel reversible BCD adder that leverages Feynman, Toffoli, Haghparast–Navi Gate (HNG), Haghparast–Navi Full Gate (HNFG), Thapliyal–Sreenivas Gate (TSG), Peres, etc., gates to achieve exceptional energy efficiency and scalability. Designed using a generic programming methodology, the adder supports seamless adaptability to varying input sizes, scaling efficiently up to 512 bits without requiring redesign. The proposed design achieves a significant reduction in quantum cost (50), garbage outputs (14), and power dissipation (24 mW), while maintaining competitive delay (1.555 ns) and gate count (11), demonstrating superior efficiency compared to existing 8-bit reversible BCD adders. These findings have significant implications for power-sensitive applications, including portable devices, Internet of Things (IoT) systems, data centers, and quantum computing architectures. This work demonstrates the feasibility of high-performance, sustainable arithmetic operations for next-generation computing systems. [ABSTRACT FROM AUTHOR]

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