Tiwari, K. S., Wahul, R. M., Shinde, S. D., Dudhedia, M. A., Gaikwad, V. P., Bhalerao, P., Gill, S. K., Chhajed, N., Daniel, C., & Gawande, S. H. (2025). Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA. Mathematical Modelling of Engineering Problems, 12(2), 730-744. https://doi.org/10.18280/mmep.120235

TIWARI, Kanchan S., WAHUL, Revati M., SHINDE, Sagar D., DUDHEDIA, Manisha A., GAIKWAD, Varsha P., BHALERAO, Pranav, GILL, Simrit Kaur, CHHAJED, Neeraj, DANIEL, Christy und GAWANDE, Shravan H., 2025. Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA. Mathematical Modelling of Engineering Problems. 1 Februar 2025. Vol. 12, no. 2, p. 730-744. DOI 10.18280/mmep.120235.

Tiwari, K. S., R. M. Wahul, S. D. Shinde, M. A. Dudhedia, V. P. Gaikwad, P. Bhalerao, S. K. Gill, N. Chhajed, C. Daniel, und S. H. Gawande. „Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA.“. Mathematical Modelling of Engineering Problems, Bd. 12, Nr. 2, Februar 2025, S. 730-44, https://doi.org/10.18280/mmep.120235.

Tiwari, Kanchan S./Wahul, Revati M./Shinde, Sagar D./Dudhedia, Manisha A./Gaikwad, Varsha P./Bhalerao, Pranav u. a.: Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA., Mathematical Modelling of Engineering Problems 2025, 730-744.

Tiwari, K.S., Wahul, R.M., Shinde, S.D., Dudhedia, M.A., Gaikwad, V.P., Bhalerao, P., Gill, S.K., Chhajed, N., Daniel, C. und Gawande, S.H. (2025), „Design and Implementation of Low Power Generic Reversible Binary-Coded Decimal Adder on Artix-7 FPGA.“, Mathematical Modelling of Engineering Problems, Vol. 12 No. 2, S. 730-744.