Treffer: Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures

Title:
Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures
Authors:
BECKER, Jürgen, LIEBAU, Nicolas, PIONTECK, Thilo, GLESNER, Manfred
Source:
FPL 2001 : field-programmable logic and applications (Belfast, 27-29 August 2001)Lecture notes in computer science. :584-589
Publisher Information:
Berlin: Springer, 2001.
Publication Year:
2001
Physical Description:
print, 20 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Conception assistée, Computer aided design, Concepción asistida, Conception circuit, Circuit design, Concepción circuito, Multidisciplinaire, Multidisciplinary, Multidisciplinario, Méthode combinatoire, Combinatorial method, Método combinatorio, Méthode optimisation, Optimization method, Método optimización, Optimisation combinatoire, Combinatorial optimization, Optimización combinatoria, Processeur tableau, Array processor, Procesador panel, Radiocommunication service mobile, Mobile radiocommunication, Radiocomunicación servicio móvil, Radiotéléphonie cellulaire, Cellular radio, Structure gros grain, Coarse grain structure, Estructura grano grueso, Système sur puce, System on chip SOC
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Darmstadt University of Technology, Institute of Microelectronic Systems, Karlstr. 15, 64283 Darmstadt, Germany
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=1019984
Rights:
Copyright 2001 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.1019984
Database:
PASCAL Archive

Weitere Informationen

Application-specific Systems-on-Chip (SoCs) introduce a set of various challenges for their interdisciplinary microelectronic implementation, from system theory (application) level over efficient CAD methods to suitable technologies, e. g. considering also reconfigurable hardware parts on different granularities. The paper sketches first major perspectives in architecture, design and application of Configurable Systems-on-Chip (CSoCs). The focus is the description of new CAD-algorithms for mapping automatized pre-synthesized IP-cores onto coarse-grain dynamically reconfigurable array architectures. Here, combinatorial optimization methods are combined with physical chip design algorithms, whereas dynamic reconfiguration of allocated hardware resources is considered.