Treffer: A Dual-VDD low power FPGA architecture

Title:
A Dual-VDD low power FPGA architecture
Authors:
GAYASEN, A, LEE, K, VIJAYKRISHNAN, N, KANDEMIR, M, IRWIN, M. J, TUAN, T
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :145-157
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 19 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Alimentation électrique, Power supply, Alimentación eléctrica, Architecture reconfigurable, Reconfigurable architectures, Chemin critique, Critical path, Recorrido crítico, Conception circuit, Circuit design, Diseño circuito, Consommation énergie électrique, Power consumption, Consommation énergie, Energy consumption, Consumo energía, Puissance faible, Low power, Potencia débil, Routage, Routing, Enrutamiento, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système temporisé, Timed system, Sistema temporizado
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, United States
Xilinx Research Labs, 2100 Logic Dr., San Jose, CA 95124, United States
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107578
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107578
Database:
PASCAL Archive

Weitere Informationen

The continuing increase in FPGA size and complexity and the emergence of sub-100nm technology have made FPGA power consumption, both dynamic and static, an important design consideration. In this work, we propose a programmable dual-VDD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-VDD to non-critical paths in the design, while assigning high-VDD to the timing critical paths in the design to meet timing constraints. We evaluate the effectiveness of different VDD assignment algorithms and architectural implementations. Our experimental results show that reducing the supply voltage selectively to the non-critical paths provides significant power savings with minimal impact on performance. One of our VDD-assignment techniques provides an average power saving of 61% across different MCNC benchmarks.