Result: Area-time efficient systolic architecture for the DCT
Title:
Area-time efficient systolic architecture for the DCT
Authors:
Source:
Advances in computer systems architecture (10th Asia-Pacific conference, ACSAC 2005, Singapore, October 24-26, 2005, proceedings)Lecture notes in computer science. :787-794
Publisher Information:
Berlin: Springer, 2005.
Publication Year:
2005
Physical Description:
print, 9 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Matériel informatique, Hardware, Ordinateurs, microordinateurs, Computers, microcomputers, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Complexité algorithme, Algorithm complexity, Complejidad algoritmo, Complexité temps, Time complexity, Complejidad tiempo, Entrée sortie, Input output, Entrada salida, Processeur pipeline, Pipeline processor, Procesador oleoducto, Retard, Delay, Retraso, Transformation cosinus discrète, Discrete cosine transforms
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
School of Computer Engineering, Nanyang Technological University, Singapore 639798, Singapore
ISSN:
0302-9743
Rights:
Copyright 2006 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.17459465
Database:
PASCAL Archive
Further Information
A reduced-complexity algorithm and its systolic architecture are presented for computation of the discrete cosine transform. The proposed scheme not only leads to a fully-pipelined regular and modular hardware, but also offers significantly higher throughput, lower latency and lower area-time complexity over the existing structures. The proposed design is devoid of complicated input/output mapping and complex control structure. Moreover, it does not have any restriction on the transform-length and it is easily scalable for higher transform-length as well.