Treffer: Low thermal budget processing for sequential 3-D IC fabrication
Title:
Low thermal budget processing for sequential 3-D IC fabrication
Authors:
Source:
I.E.E.E. transactions on electron devices. 54(4):707-714
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 16 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Basse pression, Low pressure, Baja presión, Circuit intégré, Integrated circuit, Circuito integrado, Dépôt chimique phase vapeur, Chemical vapor deposition, Depósito químico fase vapor, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Grille transistor, Transistor gate, Rejilla transistor, Oxyde grille, Gate oxide, Oxido rejilla, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Recuit faisceau laser, Laser beam annealing, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Traitement sériel, Serial processing, Procesamiento serial, Traitement thermique, Heat treatment, Tratamiento térmico, Transistor MOS complémentaire, Complementary MOS transistor, Transistor MOS complementario, CMOSFET, integrated circuit fabrication, lase annealing, low-pressure chemical vapor deposition (LPCVD)
Document Type:
Fachzeitschrift
Article
File Description:
text
Language:
English
Author Affiliations:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305, United States
IBM Almaden Research Center, San Jose, CA 95120, United States
AMBP Tech Corporation, Tonowanda, NY 14150, United States
IBM Almaden Research Center, San Jose, CA 95120, United States
AMBP Tech Corporation, Tonowanda, NY 14150, United States
ISSN:
0018-9383
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18654008
Database:
PASCAL Archive
Weitere Informationen
Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. We demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 °C low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below.