RAJENDRAN, B., SHENOY, R. S., WITTE, D. J., CHOKSHI, N. S., DELEON, R. L., TOMPA, G. S., & PEASE, R. F. W. (2007). Low thermal budget processing for sequential 3-D IC fabrication. I.E.E.E. Transactions on Electron Devices, 54(4), 707-714.
ISO-690 (author-date, English)RAJENDRAN, Bipin, SHENOY, Rohit S, WITTE, Daniel J, CHOKSHI, Nehal S, DELEON, Robert L, TOMPA, Gary S und PEASE, R. Fabian W, 2007. Low thermal budget processing for sequential 3-D IC fabrication. I.E.E.E. transactions on electron devices. 1 Januar 2007. Vol. 54, no. 4, p. 707-714.
Modern Language Association 9th editionRAJENDRAN, B., R. S. SHENOY, D. J. WITTE, N. S. CHOKSHI, R. L. DELEON, G. S. TOMPA, und R. F. W. PEASE. „Low Thermal Budget Processing for Sequential 3-D IC Fabrication“. I.E.E.E. Transactions on Electron Devices, Bd. 54, Nr. 4, Januar 2007, S. 707-14.
Mohr Siebeck - Recht (Deutsch - Österreich)RAJENDRAN, Bipin/SHENOY, Rohit S/WITTE, Daniel J/CHOKSHI, Nehal S/DELEON, Robert L/TOMPA, Gary S u. a.: Low thermal budget processing for sequential 3-D IC fabrication, I.E.E.E. transactions on electron devices 2007, 707-714.
Emerald - HarvardRAJENDRAN, B., SHENOY, R.S., WITTE, D.J., CHOKSHI, N.S., DELEON, R.L., TOMPA, G.S. und PEASE, R.F.W. (2007), „Low thermal budget processing for sequential 3-D IC fabrication“, I.E.E.E. Transactions on Electron Devices, Vol. 54 No. 4, S. 707-714.