Result: Threshold voltage shift of submicron p-channel MOSFET due to Si surface damage from plasma etching process
Title:
Threshold voltage shift of submicron p-channel MOSFET due to Si surface damage from plasma etching process
Authors:
Source:
Proceedings of the International Symposium on Dry Process (DPS 2005), Jeju, Korea, November 28-30, 2005Thin solid films. 515(12):4892-4896
Publisher Information:
Lausanne: Elsevier Science, 2007.
Publication Year:
2007
Physical Description:
print, 18 ref
Original Material:
INIST-CNRS
Subject Terms:
Crystallography, Cristallographie cristallogenèse, Electronics, Electronique, Metallurgy, welding, Métallurgie, soudage, Condensed state physics, Physique de l'état condensé, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Physique des gaz, des plasmas et des decharges electriques, Physics of gases, plasmas and electric discharges, Physique des plasmas et décharges électriques, Physics of plasmas and electric discharges, Applications des plasmas, Plasma applications, Gravure et nettoyage, Etching and cleaning, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Canal p, p channel, Canal transistor, Transistor channel, Courant drain, Drain current, Corriente dren, Courant fuite, Leakage current, Corriente escape, Electrode commande, Gates, Endommagement, Damaging, Deterioración, Gravure plasma, Plasma etching, Grabado plasma, Gravure sèche, Dry etching, Grabado seco, Interface, Interfase, Procédé voie humide, Wet process, Procedimiento vía húmeda, Procédé voie sèche, Dry process, Procedimiento vía seca, Profil dopage, Doping profile, Perfil doping, Résistance contact, Contact resistance, Resistencia contacto, Seuil tension, Voltage threshold, Umbral tensión, Silicium oxyde, Silicon oxides, Siliciure, Silicides, Siliciuro, Transistor MOSFET, MOSFET, 5277B, 8530T, Si, SiO2, Gate-induced-drain-leakage current, Plasma charging damage, Threshold voltage shift
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
School of Electrical and Electronic Engineering, Chung-Ang University, 221 Huksuk-Dong, Dongjak-Gu, Seoul 156-756, Korea, Republic of
FAM Division, DongbuAnam Semiconductor Inc., 222-1, Dodang-Dong, Wonmi-Gu, Buchoen-City, Kyungki-Do 420-712, Korea, Republic of
FAM Division, DongbuAnam Semiconductor Inc., 222-1, Dodang-Dong, Wonmi-Gu, Buchoen-City, Kyungki-Do 420-712, Korea, Republic of
ISSN:
0040-6090
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Physics of gases, plasmas and electric discharges
Physics of gases, plasmas and electric discharges
Accession Number:
edscal.18654561
Database:
PASCAL Archive
Further Information
We compared performances for transistors produced using both wet and dry etching for non-silicide processes in the CMOS technology. It was found that the dry process for non-silicide area induces the threshold voltage shifting of the pMOS transistor as well as increases the contact resistance on active region. Also, GIDL (gate-induced-drain-leakage) current has a poor junction leakage current compared with the wet etching process. Moreover, the dry etching process changes the doping profile of the P+ junction and the p-channel transistor region. The experiments showed the dry etching process generates the Si-SiO2 interface trap site due to plasma-induced damage. © 2006 Elsevier B.V. All rights reserved.