• The circuits and robust design...

Treffer: The circuits and robust design methodology of the massively parallel processor based on the matrix architecture

Title:
The circuits and robust design methodology of the massively parallel processor based on the matrix architecture
Authors:
NODA, Hideyuki, TANIZAKI, Tetsushi, ARIMOTO, Kazutami, GYOHTEN, Takayuki, DOSAKA, Katsumi, NAKAJIMA, Masami, MIZUMOTO, Katsuya, YOSHIDA, Kanako, IWAO, Takenobu, NISHIJIMA, Tetsu, OKUNO, Yoshihiro
Source:
2006 Symposium on VLSI circuitsIEEE journal of solid-state circuits. 42(4):804-812
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 7 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Matériel informatique, Hardware, Equipements d'entrée-sortie, Input-output equipment, Architecture parallèle, Parallel architectures, Calculateur SIMD, SIMD computer, Circuit intégré, Integrated circuit, Circuito integrado, Conception circuit, Circuit design, Diseño circuito, Consommation énergie électrique, Power consumption, Electronique faible puissance, Low-power electronics, Evaluation performance, Performance evaluation, Evaluación prestación, Haute performance, High performance, Alto rendimiento, Interface entrée sortie, Input output interface, Interfase entrada salida, Multimédia, Multimedia, Performance algorithme, Algorithm performance, Resultado algoritmo, Processeur 16 bits, 16 bit Processor, Procesador 16 bits, Robustesse, Robustness, Robustez, Système sur puce, System on a chip, Sistema sobre pastilla, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Virgule fixe, Fixed point, Coma fija, CMOS, SIMD, integrated circuits, low power, memory, parallel processor
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Renesas Technology Corporation, Itami, Hyogo 664-0005, Japan
ISSN:
0018-9200
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18665979
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18665979
Database:
PASCAL Archive

Weitere Informationen

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth's algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0 GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs.