NODA, H., TANIZAKI, T., ARIMOTO, K., GYOHTEN, T., DOSAKA, K., NAKAJIMA, M., MIZUMOTO, K., YOSHIDA, K., IWAO, T., NISHIJIMA, T., & OKUNO, Y. (2007, January 1). The circuits and robust design methodology of the massively parallel processor based on the matrix architecture. 42(4). New York, NY: Institute of Electrical and Electronics Engineers, 2007. Retrieved from http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665979

NODA, Hideyuki, TANIZAKI, Tetsushi, ARIMOTO, Kazutami, GYOHTEN, Takayuki, DOSAKA, Katsumi, NAKAJIMA, Masami, MIZUMOTO, Katsuya, YOSHIDA, Kanako, IWAO, Takenobu, NISHIJIMA, Tetsu and OKUNO, Yoshihiro, 2007. The circuits and robust design methodology of the massively parallel processor based on the matrix architecture. In: [online]. New York, NY: Institute of Electrical and Electronics Engineers, 2007. 1 January 2007. Available from: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665979

NODA, H., T. TANIZAKI, K. ARIMOTO, T. GYOHTEN, K. DOSAKA, M. NAKAJIMA, K. MIZUMOTO, K. YOSHIDA, T. IWAO, T. NISHIJIMA, and Y. OKUNO. The circuits and robust design methodology of the massively parallel processor based on the matrix architecture. no. 4, New York, NY: Institute of Electrical and Electronics Engineers, 2007., 2007, http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665979.

NODA, H., TANIZAKI, T., ARIMOTO, K., GYOHTEN, T., DOSAKA, K., NAKAJIMA, M., MIZUMOTO, K., YOSHIDA, K., IWAO, T., NISHIJIMA, T. and OKUNO, Y. (2007), “The circuits and robust design methodology of the massively parallel processor based on the matrix architecture”, in , Vol. 42, New York, NY: Institute of Electrical and Electronics Engineers, 2007., available at: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665979.