Result: The 65-nm 16-MB shared on-die L3 cache for the dual-core intel xeon processor 7100 series
Title:
The 65-nm 16-MB shared on-die L3 cache for the dual-core intel xeon processor 7100 series
Authors:
Source:
2006 Symposium on VLSI circuitsIEEE journal of solid-state circuits. 42(4):846-852
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 6 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Matériel informatique, Hardware, Ordinateurs, microordinateurs, Computers, microcomputers, Antémémoire, Cache memory, Antememoria, Architecture ordinateur, Computer architecture, Arquitectura ordenador, Circuit intégré, Integrated circuit, Circuito integrado, Conception circuit, Circuit design, Diseño circuito, Défaillance, Failures, Fallo, Electronique faible puissance, Low-power electronics, Fiabilité, Reliability, Fiabilidad, Matrice formage, Die, Matriz formadora, Microprocesseur, Microprocessor, Microprocesador, Mémoire accès direct statique, Static random access memory, Mémoire accès direct, Random access memory, Memoria acceso directo, Processeur, Processor, Procesador, Transistor, computer architecture, manufacturability, microprocessor, on-die cache, power reduction, reliability, test
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Intel Corporation, Santa Clara, CA 95052, United States
ISSN:
0018-9200
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18665984
Database:
PASCAL Archive
Further Information
The 16-way set associative, single-ported 16-MB cache for the Dual-Core Intel Xeon Processor 7100 Series uses a 0.624 μm2 cell in a 65-nm 8-metal technology. Low power techniques are implemented in the L3 cache to minimize both leakage and dynamic power. Sleep transistors are used in the SRAM array and peripherals, reducing the cache leakage by more than 2X. Only 0.8% of the cache is powered up for a cache access. Dynamic cache line disable (Intel Cache Safe Technology) with a history buffer protects the cache from latent defects and infant mortality failures.