CHANG, J., MING HUANG, RUSU, S., SRIVASTAVA, D., SHOEMAKER, J., BENOIT, J., CHEN, S.-L., WEI CHEN, SIUFU CHIU, GANESAN, R., LEONG, G., & LUKKA, V. (2007, January 1). The 65-nm 16-MB shared on-die L3 cache for the dual-core intel xeon processor 7100 series. 42(4). New York, NY: Institute of Electrical and Electronics Engineers, 2007. Retrieved from http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665984

CHANG, Jonathan, MING HUANG, RUSU, Stefan, SRIVASTAVA, Durgesh, SHOEMAKER, Jonathan, BENOIT, John, CHEN, Szu-Liang, WEI CHEN, SIUFU CHIU, GANESAN, Raghuraman, LEONG, Gloria and LUKKA, Venkata, 2007. The 65-nm 16-MB shared on-die L3 cache for the dual-core intel xeon processor 7100 series. In: [online]. New York, NY: Institute of Electrical and Electronics Engineers, 2007. 1 January 2007. Available from: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665984

CHANG, J., MING HUANG, S. RUSU, D. SRIVASTAVA, J. SHOEMAKER, J. BENOIT, S.-L. CHEN, WEI CHEN, SIUFU CHIU, R. GANESAN, G. LEONG, and V. LUKKA. The 65-nm 16-MB shared on-die L3 cache for the dual-core intel xeon processor 7100 series. no. 4, New York, NY: Institute of Electrical and Electronics Engineers, 2007., 2007, http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665984.

CHANG, J., MING HUANG, RUSU, S., SRIVASTAVA, D., SHOEMAKER, J., BENOIT, J., CHEN, S.-L., WEI CHEN, SIUFU CHIU, GANESAN, R., LEONG, G. and LUKKA, V. (2007), “The 65-nm 16-MB shared on-die L3 cache for the dual-core intel xeon processor 7100 series”, in , Vol. 42, New York, NY: Institute of Electrical and Electronics Engineers, 2007., available at: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18665984.