Result: Test scheduling for built-in self-tested embedded SRAMs with data retention faults

Title:
Test scheduling for built-in self-tested embedded SRAMs with data retention faults
Authors:
XU, Q, WANG, B, IVANOV, A, YOUNG, F. Y
Source:
Selected best papers from ETS'06IET computers & digital techniques (Print). 1(3):256-264
Publisher Information:
Stevenage: Institution of Engineering and Technology, 2007.
Publication Year:
2007
Physical Description:
print, 31 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Computer science, Informatique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Algorithme, Algorithm, Algoritmo, Autotest, Built in self test, Autoprueba, Circuit intégré, Integrated circuit, Circuito integrado, Consommation énergie électrique, Power consumption, Electronique faible puissance, Low-power electronics, Mémoire accès direct statique, Static random access memory, Mémoire accès direct, Random access memory, Memoria acceso directo, Ordonnancement, Scheduling, Reglamento, Temps calcul, Computation time, Tiempo computación
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong-Kong
AMD, AMD One Place, Sunnyvale, CA, United States
Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, B.C., V6T 1Z4, Canada
ISSN:
1751-8601
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18789659
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18789659
Database:
PASCAL Archive

Further Information

The test scheduling problem for built-in self-tested embedded SRAMs (e-SRAMs) when data retention faults (DRFs) are considered is addressed here. We proposed a 'retention-aware' test power model by taking advantage of the fact that there is near-zero test power during the pause time for testing DRFs. The proposed test scheduling algorithm then utilises this new test power model to minimise the total testing time of e-SRAMs while not violating given power constraints, by scheduling some e-SRAM tests during the pause time of DRF tests. Without losing generality, we consider both cases where the pause time for DRFs is fixed and cases where it can be varied. Experimental results show that the proposed 'retention-aware' test power model and the corresponding test scheduling algorithm can reduce the testing time of e-SRAMs significantly with negligible computational time.