Result: Reliability screening of high-k dielectrics based on voltage ramp stress
Title:
Reliability screening of high-k dielectrics based on voltage ramp stress
Authors:
Source:
14TH Workshop on dielectrics in microelectronics (WoDiM 2006)Microelectronics and reliability. 47(4-5):513-517
Publisher Information:
Oxford: Elsevier, 2007.
Publication Year:
2007
Physical Description:
print, 8 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Chronométrie, Time measurement, Cronometría, Contrainte électrique, Electric stress, Tensión eléctrica, Diélectrique permittivité élevée, High k dielectric, Dieléctrico alta constante dieléctrica, Fiabilité, Reliability, Fiabilidad, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Qimonda AG, Otto Hahn Ring 6, 81739 Munich, Germany
IMEC, Otto Hahn Ring 6, 81739 Munich, Germany
ESA T KU-Leuven, Otto Hahn Ring 6, 81739 Munich, Germany
Infineon Technologies AG, Otto Hahn Ring 6, 81739 Munich, Germany
IMEC, Otto Hahn Ring 6, 81739 Munich, Germany
ESA T KU-Leuven, Otto Hahn Ring 6, 81739 Munich, Germany
Infineon Technologies AG, Otto Hahn Ring 6, 81739 Munich, Germany
ISSN:
0026-2714
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18790324
Database:
PASCAL Archive
Further Information
High-k development moves towards integration into CMOS processes rising attention for the reliability assessment. In this paper, the methodology for reliability screening is discussed based on constant voltage stress and voltage ramp stress. It will be shown that both procedures yield equivalent results and the determined reliability parameters are compatible. Better control of the overall measurement time favours the voltage ramp stress as preferred fast screening method for integration of high-k dielectrics.