Treffer: Reliability of HTO based high-voltage gate stacks for flash memories
Title:
Reliability of HTO based high-voltage gate stacks for flash memories
Authors:
Source:
14TH Workshop on dielectrics in microelectronics (WoDiM 2006)Microelectronics and reliability. 47(4-5):615-618
Publisher Information:
Oxford: Elsevier, 2007.
Publication Year:
2007
Physical Description:
print, 6 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuit intégré, Integrated circuit, Circuito integrado, Contrainte électrique, Electric stress, Tensión eléctrica, Endommagement, Damaging, Deterioración, Essai électrique, Electrical test, Ensayo eléctrico, Fiabilité, Reliability, Fiabilidad, Grille transistor, Transistor gate, Rejilla transistor, Haute performance, High performance, Alto rendimiento, Haute tension, High voltage, Alta tensión, Multicouche, Multiple layer, Capa múltiple, Mémoire flash, Flash memory, Memoria flash, Optimisation, Optimization, Optimización, Piégeage porteur charge, Charge carrier trapping, Captura portador carga, Relaxation, Relajación, Tension grille, Gate voltage
Document Type:
Konferenz
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Tower Semiconductor Ltd., P.O. Box 619, Migdal HaEmek 23105, Israel
ISSN:
0026-2714
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18790346
Database:
PASCAL Archive
Weitere Informationen
We report on the excellent reliability performance of high-voltage (HV) gate stacks comprised of a thin thermal oxide and a thicker HTO layer. Time-to-breakdown of the developed stacks exceeded corresponding values for thermal HV oxides of the same thickness. Peculiarities of current relaxation in course of electrical stress tests are interpreted by injected charge trapping in HTO and new trap generation. Charge trapping in optimized HTO is low and guarantees reliable device operation.