Result: Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

Title:
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Authors:
BRAJESH KUMAR KAUSHIK, SARKAR, Sankar, AGARWAL, R. P
Source:
Integration (Amsterdam). 40(4):394-405
Publisher Information:
Amsterdam: Elsevier Science, 2007.
Publication Year:
2007
Physical Description:
print, 17 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Etude théorique. Analyse et conception des circuits, Theoretical study. Circuits analysis and design, Analyse forme onde, Waveform analysis, Circuit RLC, RLC circuit, Circuito RLC, Circuit intégré, Integrated circuit, Circuito integrado, Evaluation performance, Performance evaluation, Evaluación prestación, Excitateur, Driver, Excitador, Interconnexion, Interconnection, Interconexión, Ligne contact, Contact line, Línea contacto, Loi puissance, Power law, Ley poder, Modélisation, Modeling, Modelización, Méthode analytique, Analytical method, Método analítico, Onduleur, Inverter, Ondulador, Programme SPICE, SPICE, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Temps retard, Delay time, Tiempo retardo, Tension sortie, Output voltage, Voltage salida, Distributed RLC interconnect, Interconnect modeling, Propagation delay
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Department of Electronics and Computer Engineering. Indian Institute of Technology-Roorkee, Roorkee, Uttaranchal 247667, India
ISSN:
0167-9260
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18819455
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18819455
Database:
PASCAL Archive

Further Information

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.