Result: Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications

Title:
Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications
Authors:
ASENOV, A, KALNA, K, THAYNE, I, HILL, R. J. W
Source:
INFOS 2007: Proceedings of the 15th Biennial Conference on Insulating Films on Semiconductors, June 20-23, 2007, Glyfada Athens, GreeceMicroelectronic engineering. 84(9-10):2398-2403
Publisher Information:
Amsterdam: Elsevier Science, 2007.
Publication Year:
2007
Physical Description:
print, 23 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Interfaces, Dispositifs à structure composée, Compound structure devices, Transistors, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Composé III-V, III-V compound, Compuesto III-V, Contact ohmique, Ohmic contact, Contacto óhmico, Diélectrique permittivité élevée, High k dielectric, Dieléctrico alta constante dieléctrica, Electronique faible puissance, Low-power electronics, Evaluation performance, Performance evaluation, Evaluación prestación, Fiabilité, Reliability, Fiabilidad, Haute performance, High performance, Alto rendimiento, Hétérostructure, Heterostructures, Miniaturisation, Miniaturization, Miniaturización, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Méthode numérique, Numerical method, Método numérico, Méthode élément fini, Finite element method, Método elemento finito, Résistance contact, Contact resistance, Resistencia contacto, Seuil tension, Voltage threshold, Umbral tensión, Simulateur, Simulator, Simulador, Simulation numérique, Numerical simulation, Simulación numérica, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Transistor MOSFET, MOSFET, Transistor mobilité électron élevée, High electron mobility transistor, Transistor movibilidad elevada electrones, CMOS, Implant free III-V MOSFETs, Monte Carlo simulations, high-K gate dielectric
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Dept. Electronics & Elec. Eng., University of Glasgow, Glasgow G12 8LT, Scotland, United Kingdom
ISSN:
0167-9317
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18853589
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18853589
Database:
PASCAL Archive

Further Information

The potential of implant free III-V MOSFETs for high performance, low power nano-CMOS applications is studied using Monte Carlo (MC) device simulations. The viability of this III-V MOSFET architecture is first demonstrated by presenting experimental results from implant free III-V MOSFETs fabricated at Glasgow. The measured 1μm gate length implant free transistors feature high-K gate dielectric, metal gate and low resistance ohmic contacts. They have a positive threshold voltage VT = 0.1 V and deliver a drive current Ion, = 325 μA/μm at VG = VD = 2 V. The Glasgow finite element heterostructure Monte Carlo device simulator has been carefully calibrated against HEMTs with low and high In content in the channel fabricated at Glasgow and transport data measured on implant free layer structures with high-K gate dielectric grown at Glasgow and Freescale. The performance of implant free III-V MOSFETs with low In content in the channel is simulated and compared for aggressively scaled devices with channel lengths below 30 nm.