• Statistical placement for FPGA...

Result: Statistical placement for FPGAs considering process variation

Title:
Statistical placement for FPGAs considering process variation
Authors:
LIN, Y, HUTTON, M, HE, L
Source:
IET computers & digital techniques (Print). 1(4):267-275
Publisher Information:
Stevenage: Institution of Engineering and Technology, 2007.
Publication Year:
2007
Physical Description:
print, 24 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Computer science, Informatique, Telecommunications, Télécommunications, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Algorithme, Algorithm, Algoritmo, Chemin critique, Critical path, Recorrido crítico, Circuit intégré, Integrated circuit, Circuito integrado, Circuit à la demande, Custom circuit, Circuito integrato personalizado, Etude statistique, Statistical study, Estudio estadístico, Evaluation performance, Performance evaluation, Evaluación prestación, Microélectronique, Microelectronics, Microelectrónica, Modem, Módem, Réseau porte programmable, Field programmable gate array, Red puerta programable
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Electrical Engineering Department, UCLA, Los Angeles, CA 90095, United States
Altera Corporation, San Jose, CA 95134, United States
ISSN:
1751-8601
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18923545
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18923545
Database:
PASCAL Archive

Further Information

Process variations affecting timing and power is an important issue for modem integrated circuits in nanometre technologies. Field programmable gate arrays (FPGA) are similar to application-specific integrated circuit (ASIC) in their susceptibility to these issues, but face unique challenges in that critical paths are unknown at test time. The first in-depth study on applying statistical timing analysis with cross-chip and on-chip variations to speed-binning and guard-banding in FPGAs has been presented. Considering the uniqueness of re-programmability in FPGAs, the effects of timing-model with guard-banding and speed-binning on statistical performance and timing yield are quantified. A new variation aware statistical placement, which is the first statistical algorithm for FPGA layout and achieves a yield loss of 29.7% of the original yield loss with guard-banding and a yield loss of 4% of the original one with speed-binning for Microelectronics Center of North Carolina (MCNC) and Quartus University Interface Program (QUIP) designs, has also been developed.