Result: In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations

Title:
In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations
Authors:
EIREINER, Matthias, HENZLER, Stephan, GEORGAKOS, Georg, BERTHOLD, Joerg, SCHMITT-LANDSIEDEL, Doris
Source:
ESSCIRC 2006IEEE journal of solid-state circuits. 42(7):1583-1592
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 18 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Bistable, Biestable, Commutateur semiconducteur puissance, Power semiconductor switches, Correction erreur, Error correction, Corrección error, Détection erreur, Error detection, Detección error, In situ, Matrice formage, Die, Matriz formadora, Méthode Monte Carlo, Monte Carlo method, Método Monte Carlo, Régime dynamique, Dynamic conditions, Régimen dinámico, Régulation tension, Voltage regulation, Regulación voltaje, Simulation numérique, Numerical simulation, Simulación numérica, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Temps retard, Delay time, Tiempo retardo, Adaptive supply voltage (ASV), Razor flip-flop, crystal ball flip-flop, dynamic voltage scaling (DVS), error detection and correction, in-situ characterization, local supply voltage assignment
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Institute for Technical Electronics, Technical University of Munich, 80290 Munich, Germany
Infineon Technologies AG, 85579 Neubiberg, Germany
ISSN:
0018-9200
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18943693
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18943693
Database:
PASCAL Archive

Further Information

A method is proposed to compensate for local delay variations by adjusting the supply voltage of individual circuit blocks. In-situ characterization of sub-blocks allows for voltage adjustment with minimum safety margin. Different strategies and circuit techniques for in-situ delay characterization of sub-blocks are described and compared. A dual VDD /power switch scheme is proposed for discrete voltage assignment to individual sub-blocks. Experimental results are presented for a test module based on an ARM9 core, fabricated in 130-nm CMOS. Yield improvement and power reduction capabilities are demonstrated by Monte Carlo simulations. For a typical setting, a reduction of 10% in power can be achieved with the proposed dual VDD/power switch concept. Using more than two supply voltages is shown to produce only small additional power savings at the price of high area overhead. The effect of the proposed scheme increases with increasing intra-die variability, which makes it suitable especially for future technologies.