Result: Watermark-induced High-density via failures in submicron CMOS fabrication (May 2006)
Title:
Watermark-induced High-density via failures in submicron CMOS fabrication (May 2006)
Authors:
Source:
IEEE transactions on semiconductor manufacturing. 20(3):195-200
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 4 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Densité élevée, High density, Densidad elevada, Défaillance, Failures, Fallo, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Pastille électronique, Wafer, Pastilla electrónica, Polissage mécanochimique, Chemical mechanical polishing, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Via oxide, W plug
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Systems on Silicon Manufacturing Company, Singapore 519527, Singapore
ISSN:
0894-6507
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18990963
Database:
PASCAL Archive
Further Information
High via resistance was detected in the high-density via structure in our 0.15-μm back-end-of-line (BEOL) yield monitoring test vehicle. A localized insulating layer was found on top of the plug in test vehicle causing high via resistance. The failure was attributed to watermark-induced contaminants on top of the W plug. It was shown that the failure could be avoided by eliminating watermark formation on the wafer in the post-chemical-mechanical polishing scrub process.