Result: Yield learning and process optimization on 65-nm CMOS technology accelerated by the use of short flow test die
Title:
Yield learning and process optimization on 65-nm CMOS technology accelerated by the use of short flow test die
Authors:
Source:
IEEE transactions on semiconductor manufacturing. 20(3):201-207
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 12 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Apprentissage, Learning, Aprendizaje, Circuit intégré, Integrated circuit, Circuito integrado, Conception pour fabrication, Design for manufacture, Etude cas, Case study, Estudio caso, Interconnexion, Interconnection, Interconexión, Matrice formage, Die, Matriz formadora, Optimisation, Optimization, Optimización, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Technologie isolation, Insulation technology, Tecnología aislamiento, Technologie tranchée, Trench technology, Tecnología trinchera, Design for manufacturability (DFM), short flow test die, yield optimization, yield ramp
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Texas Instruments Inc, Dallas, TX 75243, United States
ISSN:
0894-6507
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18990964
Database:
PASCAL Archive
Further Information
-Short loop test flows have been commonly used in back-end-of-line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation and gate and premetal dielectric/contact loops of a 65-nm process technology in addition to the BEOL. These test chips have been used to quickly identify and eliminate random and systematic defect mechanisms and generate a robust process flow, thus accelerating the rate of yield learning.