DEBORD, J. R. D., & SRIDHAR, N. (2007, January 1). Yield learning and process optimization on 65-nm CMOS technology accelerated by the use of short flow test die. 20(3). New York, NY: Institute of Electrical and Electronics Engineers, 2007. Retrieved from http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18990964
ISO-690 (author-date, English)DEBORD, Jeffrey R. D and SRIDHAR, Nagarajan, 2007. Yield learning and process optimization on 65-nm CMOS technology accelerated by the use of short flow test die. In: [online]. New York, NY: Institute of Electrical and Electronics Engineers, 2007. 1 January 2007. Available from: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18990964
Modern Language Association 9th editionDEBORD, J. R. D., and N. SRIDHAR. Yield learning and process optimization on 65-nm CMOS technology accelerated by the use of short flow test die. no. 3, New York, NY: Institute of Electrical and Electronics Engineers, 2007., 2007, http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18990964.
Mohr Siebeck - Recht (Deutsch - Österreich)Emerald - Harvard
DEBORD, J.R.D. and SRIDHAR, N. (2007), “Yield learning and process optimization on 65-nm CMOS technology accelerated by the use of short flow test die”, in , Vol. 20, New York, NY: Institute of Electrical and Electronics Engineers, 2007., available at: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18990964.