• Voltage contrast for gate-leak...

Result: Voltage contrast for gate-leak failures detected by electron beam inspection

Title:
Voltage contrast for gate-leak failures detected by electron beam inspection
Authors:
FUJIYOSHI, Katsuhiro, SAWAI, Koetsu, INOUE, Kazutaka, SAIKI, Keiichi, SAKURAI, Koichi
Source:
IEEE transactions on semiconductor manufacturing. 20(3):208-214
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 21 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Essais, mesure, bruit et fiabilité, Testing, measurement, noise and reliability, Appareillage électronique et fabrication. Composants passifs, circuits imprimés, connectique, Electronic equipment and fabrication. Passive components, printed wiring boards, connectics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Dispositifs diélectriques et dispositifs à base de verre et de solides amorphes, Dielectric, amorphous and glass solid devices, Analyse dommage, Failure analysis, Análisis avería, Circuit intégré, Integrated circuit, Circuito integrado, Condensateur, Capacitor, Condensador, Dispositif logique, Logic devices, Disruption électrique, Electric breakdown, Disrupción eléctrica, Défaillance, Failures, Fallo, Détection fuite, Leak detection, Detección fuga, Electrode commande, Gates, Explorateur faisceau, Beam scanners, Fabrication circuit intégré, Integrated circuit manufacture, Faisceau électronique, Electron beam, Haz electrónico, Microscopie électronique balayage, Scanning electron microscopy, Microscopía electrónica barrido, Mémoire accès direct statique, Static random access memory, Mémoire accès direct, Random access memory, Memoria acceso directo, Résistance électrique, Resistor, Resistencia eléctrica(componente), Temps exécution, Execution time, Tiempo ejecución, Dielectric breakdown, SRAM chips, electron beams, failure analysis (FA), inspection, integrated circuit (IC) manufacture, leak detection, logic devices, voltage measurement
Time:
0779
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Renesas Technology Corporation, Ibaraki 312-8504, Japan
Renesas Semiconductor Engineering Corporation, Ehime 793-8501, Japan
ISSN:
0894-6507
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18990965
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18990965
Database:
PASCAL Archive

Further Information

We examine a technique for enhancing the voltage contrast (VC) of a failure analysis (FA) tool, defect review scanning electron microscope (DR-SEM). For an SRAM, we demonstrate a dependence of gate-leak VC on the relative angle (RA) between the direction of beam scanning by the FA tool and the lengthwise direction of the gate electrode. Experimental results show that better VC results are obtained when RA is zero, in other words, a beam's scan-line is parallel with the SRAM gate. We propose a simple qualitative resistor-capacitor model to explain this phenomenon. With the help of this VC enhancement technique of the FA tool, we could tune the electron beam inspection (EBI) recipe to an appropriate condition quicker. The cycle time of EBI recipe tuning was shortened from five to two days. As a result, correct EBI evaluation results of countermeasure experiments led us to a yield enhancement solution within a shorter period of time.