Treffer: Influence of circuit pattern layout on characteristics of interface-modified ramp-edge junctions

Title:
Influence of circuit pattern layout on characteristics of interface-modified ramp-edge junctions
Authors:
WAKANA, Hironori, ADACHI, Seiji, TSUBONE, Koji, TARUTANI, Yoshinobu, NAKAYAMA, Kohei, OSHIKUBO, Yasuo, TANABE, Keiichi
Source:
The 2006 applied superconductivity conference, Seattle, WA, August 27-September 1, 2006IEEE transactions on applied superconductivity. 17(2):229-232
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 17 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs supraconducteurs, Superconducting devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Electroénergétique, Electrical power engineering, Réseaux et lignes électriques, Power networks and lines, Raccordement des usagers. Installations intérieures, Users connections and in door installation, Circuit intégré supraconducteur, Superconducting integrated circuits, Circuit logique supraconducteur, Superconducting logic circuits, Densité courant critique, Critical current density, Densidad corriente crítica, Electronique quantique, Quantum electronics, Implantation circuit, Circuit layout, Implantation(topométrie), Layout, Implantación(topometría), Inductance, Inductancia, Jonction Josephson, Josephson junction, Unión Josephson, Jonction rampe, Step edge junction, Unión rampa, Logique quantique, Quantum logic, Lógica cuántica, Procédé fabrication, Manufacturing process, Procedimiento fabricación, Raccordement, Connection, Conexión, Supraconducteur haute température, High temperature superconductor, Supraconductor alta temperatura, Surface contact, Contact surface, Superficie contacto, Trou interconnexion, Via hole, Agujero interconexión, High-temperature superconductor, SFQ circuit.,, ramp-edge structure
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Superconductivity Research Laboratory, ISTEC, 10-13, Shinonome 1-chome, Koto-ku, Tokyo 135-0062, Japan
ISSN:
1051-8223
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19010182
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electrical engineering. Electroenergetics

Electronics
Accession Number:
edscal.19010182
Database:
PASCAL Archive

Weitere Informationen

-We have developed a fabrication process for single flux quantum (SFQ) circuits including a superconducting ground plane and interface-modified ramp-edge Josephson junctions. We found that the critical current density (Jc) for individual junctions in a circuit was influenced by the circuit pattern layout. The dependence of the Ic value for 5-/μm-width junctions on the base-electrode size (width and length) and the contact-hole area was carefully examined. We obtained 1-sigma Jc spreads less than 8% for junctions in actual circuits by employing a new circuit pattern layout, containing separated base-electrodes with almost the same size. We also employed connection of the separated base-electrodes by the counter-layer to reduce parasitic inductance. By employing. new layouts based on the separated base-electrode layout (SBL) method, control of Ic values by changing the junction width was readily achieved.