WAKANA, H., ADACHI, S., TSUBONE, K., TARUTANI, Y., NAKAYAMA, K., OSHIKUBO, Y., & TANABE, K. (2007, January 1). Influence of circuit pattern layout on characteristics of interface-modified ramp-edge junctions. 17(2). New York, NY: Institute of Electrical and Electronics Engineers, 2007. Retrieved from http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=19010182
ISO-690 (author-date, English)WAKANA, Hironori, ADACHI, Seiji, TSUBONE, Koji, TARUTANI, Yoshinobu, NAKAYAMA, Kohei, OSHIKUBO, Yasuo and TANABE, Keiichi, 2007. Influence of circuit pattern layout on characteristics of interface-modified ramp-edge junctions. In: [online]. New York, NY: Institute of Electrical and Electronics Engineers, 2007. 1 January 2007. Available from: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=19010182
Modern Language Association 9th editionWAKANA, H., S. ADACHI, K. TSUBONE, Y. TARUTANI, K. NAKAYAMA, Y. OSHIKUBO, and K. TANABE. Influence of circuit pattern layout on characteristics of interface-modified ramp-edge junctions. no. 2, New York, NY: Institute of Electrical and Electronics Engineers, 2007., 2007, http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=19010182.
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WAKANA, H., ADACHI, S., TSUBONE, K., TARUTANI, Y., NAKAYAMA, K., OSHIKUBO, Y. and TANABE, K. (2007), “Influence of circuit pattern layout on characteristics of interface-modified ramp-edge junctions”, in , Vol. 17, New York, NY: Institute of Electrical and Electronics Engineers, 2007., available at: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=19010182.