• Minimization of parasitic indu...

Treffer: Minimization of parasitic inductances in SFQ circuits using over-and under-ground planes

Title:
Minimization of parasitic inductances in SFQ circuits using over-and under-ground planes
Authors:
MYOREN, Hiroaki, KISHITA, Noriaki, TAINO, Tohru, TAKADA, Susumu
Source:
The 2006 applied superconductivity conference, Seattle, WA, August 27-September 1, 2006IEEE transactions on applied superconductivity. 17(2):462-465
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 9 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs magnétiques, Magnetic devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Transformateurs et inductances, Transformers and inductors, Bobine inductance, Inductor, Circuit intégré supraconducteur, Superconducting integrated circuits, Circuit logique supraconducteur, Superconducting logic circuits, Circuit logique, Logic circuit, Circuito lógico, Dépendance fréquence, Frequency dependence, Electronique quantique, Quantum electronics, Forme rectangulaire, Rectangular shape, Forma rectangular, Inductance, Inductancia, Logique quantique, Quantum logic, Lógica cuántica, 2-branch D-FF, Over- and under-ground planes, SFQ logic circuits, parasitic inductance
Document Type:
Konferenz Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Saitama University, 255 Shimo-okubo, Sakura-ku, Saitama 338-8570, Japan
ISSN:
1051-8223
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19010235
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electrical engineering. Electroenergetics

Electronics
Accession Number:
edscal.19010235
Database:
PASCAL Archive

Weitere Informationen

We designed the single-flux-quantum (SFQ) circuits that were fabricating using the NEC 2.5 kA/cm2 standard process that has four Nb layers. Before designing circuits with two ground planes, we estimated sheet inductances of the base and counter planes using simple rectangular-shape inductors. Estimated sheet inductance of the base plane was 0.75 of the original value for the circuits with only under-ground plane. For the counter plane, sheet inductance was estimated to be 0.55 of the original value. We designed a 2-branch D-FF gate and fabricated SFQ circuits including the 2-branch D-FF using the NEC standard process. Parasitic inductances of the counter layer in the 2-branch D-FF were effectively minimized using two ground planes and frequency dependences of the lower bias margin were improved.