Result: Implementation and experimental evaluation of a cryocooled system prototype for high-throughput SFQ digital applications

Title:
Implementation and experimental evaluation of a cryocooled system prototype for high-throughput SFQ digital applications
Authors:
HASHIMOTO, Yoshihito, YOROZU, Shinichi, MIYAZAKI, Toshiyuki, KAMEDA, Yoshio, SUZUKI, Hideo, YOSHIKAWA, Nobuyuki
Source:
The 2006 applied superconductivity conference, Seattle, WA, August 27-September 1, 2006IEEE transactions on applied superconductivity. 17(2):546-551
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2007.
Publication Year:
2007
Physical Description:
print, 17 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Assemblage circuit intégré, Integrated circuit bonding, Chambre à vide, Vacuum chamber, Cámara de vacío, Circuit cryogénique, Cryogenic circuit, Circuito criogénico, Circuit intégré supraconducteur, Superconducting integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique supraconducteur, Superconducting logic circuits, Conception système, System design, Concepción sistema, Contact bosse, Solder bump, Contacto con bollos, Estimation paramètre, Parameter estimation, Estimación parámetro, Grande vitesse, High speed, Gran velocidad, Implémentation, Implementation, Implementación, Logique quantique, Quantum logic, Lógica cuántica, Module multipuce, Multichip module, Modulo multipulga, Méthode section divisée, Multistage method, Paramètre s, s parameter, Parámetro s, Prototype, Prototipo, Puce à bosses, Flip-chip, Puce électronique, Chip, Pulga electrónica, Suite pseudoaléatoire, Pseudorandom sequence, Sucesión seudo aleatoria, Supraconducteur, Superconducting materials, Supraconductor, Taux erreur bit, Bit error rate, Tasa error bit, Cryocooler, SFQ, cryopackaging, integrated circuit, multi-chip module, superconductor
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
International Superconductivity Technology Center (ISTEC), Tsukuba, Ibaraki 305-8501, Japan
JST, Tsukuba, Japan
ISTEC, Tokyo, Japan
Yokohama National University, Yokohama, Japan
ISSN:
1051-8223
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19010255
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.19010255
Database:
PASCAL Archive

Further Information

We report on development of a cryocooled system prototype for high-throughput single flux quantum (SFQ) digital applications. The system was designed to have 32 I/O links with a bandwidth of 10 Gbps/port. An SFQ multi-chip module (MCM), double mu-metal magnetic shields, a 40-K radiation shield, customized GaAs cryogenic amplifiers, a 32-pin wide-bandwidth cryo-probe, and 32 I/O cables were packaged in a vacuum chamber together with a two-stage 4-K 1-W Gifford-McMahon (G-M) cryocooler. S-parameter measurements showed that the analog bandwidth of the I/O link was 23 GHz. We demonstrated high-speed cryocooled operation of a test module, in which a 5 mm x 5 mm SFQ circuit chip was flip-chip bonded on a 16 mm × 16 mm MCM carrier with Φ30 μm InSn bump bonds, at bit rates up to 12.5 Gbps. Measured bit error rate (BER) was less than 10-12 for a 1023 - 1 pseudorandom bit sequence (PRBS) at 10 Gbps.