Result: Reaching fast code faster : Using modeling for efficient software thread integration on a VLIW DSP

Title:
Reaching fast code faster : Using modeling for efficient software thread integration on a VLIW DSP
Authors:
SO, Won, DEAN, Alexander G
Source:
CASES 2006 (International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 22-25, 2006, Seoul, Korea, embedded systems week 2006). :13-23
Publisher Information:
New York NY: ACM Press, 2006.
Publication Year:
2006
Physical Description:
print, 33 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Informatique théorique, Theoretical computing, Théorie des langages et analyse syntaxique, Language theory and syntactical analysis, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Ajustement modèle, Model matching, Ajustamiento modelo, Calculateur embarqué, Boarded computer, Calculador embarque, Classification hiérarchique, Hierarchical classification, Clasificación jerarquizada, Compilateur, Compiler, Compilador, Compilation, Compilación, Mise à jour, Updating, Actualización, Modélisation, Modeling, Modelización, Mot instruction très long, Very long instruction word, Palabra instrucción muy larga, Optimisation compilateur, Compiler optimization, Optimización compiladora, Processus léger (logiciel), Thread (software), Proceso ligero (logicial), Ramification, Branching, Ramificación, Retard, Delay, Retraso, Traitement parallèle, Parallel processing, Tratamiento paralelo
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Center for Embedded Systems Research Department of Electrical and Computer Engineering North Carolina State University, Raleigh, NC 27695-7256, United States
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=19105478
Rights:
Copyright 2007 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Accession Number:
edscal.19105478
Database:
PASCAL Archive

Further Information

When integrating software threads together to boost performance on a processor with instruction-level parallel processing support, it is rarely clear which code regions should be aligned and integrated, and which regions should be left alone. This problem grows even worse on a modern VLIW DSP due to complicating factors in both the hardware and compiler: software pipelining, predication, branch delay slots, load delay slots and limited resources. As a result, finding an effective integration strategy requires extensive iteration through the integrate/compile/analyze sequence. In this paper we introduce methods to quantitatively estimate the performance benefit from the integration of multiple software threads. We use resource modeling, consider register pressure and compensate for compiler optimizations. This enables different scenarios to be compared and ranked. We then use these estimates to guide integration by concentrating on the most beneficial scenario. Information from each iteration of compilation is used to update the rankings of scenarios. We find that our modeling methods combined with limited compilation quickly find the best integration scenario without requiring exhaustive integration.