Result: 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Title:
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing
Authors:
SEKIGUCHI, Tomonori, ONO, Kazuo, KOTABE, Akira, YANAGAWA, Yoshimitsu
Source:
Special Issue on the 2010 Symposium on VLSI CircuitsIEEE journal of solid-state circuits. 46(4):828-837
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2011.
Publication Year:
2011
Physical Description:
print, 13 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Etude théorique. Analyse et conception des circuits, Theoretical study. Circuits analysis and design, Stockage et lecture de l'information, Storage and reproduction of information, Mémoires de masse magnétiques et optiques, Magnetic and optical mass memories, Mémoire accès direct, Random access memory, Memoria acceso directo, Mémoire non volatile, Non volatile memory, Memoria no volátil, Bus de données, Data bus, Bus datos, Capacité parasite, Spurious capacity, Capacidad parásita, Circuit faible bruit, Low noise circuit, Circuito débil ruido, Circuit intégré, Integrated circuit, Circuito integrado, Conception compacte, Compact design, Concepción compacta, Consommation électricité, Electric power consumption, Consumo electricidad, Dispositif à mémoire, Memory devices, Empilement, Stacking, Apilamiento, Evaluation performance, Performance evaluation, Evaluación prestación, Interconnexion, Interconnection, Interconexión, Mémoire accès direct dynamique, Dynamic random access memory, Mémoire répartie, Distributed memory, Memoria compartida, Processeur, Processor, Procesador, Silicium, Silicon, Silicio, Simulation circuit, Circuit simulation, Système autonome, Autonomous system, Sistema autónomo, Traitement pipeline, Pipeline processing, Trou interconnexion, Via hole, Agujero interconexión, 3D interconnect, DRAM, TSV, multi-core, pipeline
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Hitachi Europe Ltd. European Research and Development Centre, Maidenhead, Berkshire SL6 8YA, United Kingdom
Hitachi, Ltd., Central Research Laboratory, Measurement Systems Research Department, Kokubunji, Tokyo 185-8601, Japan
ISSN:
0018-9200
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=24154048
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.24154048
Database:
PASCAL Archive

Further Information

Aiming to resolve memory bottlenecks in multi-core system, novel 1-Tbyte/s 1-Gbit DRAM architecture based on a multi-core configuration and 3-D interconnects was developed. The DRAM stacked on a multi-core CPU has 512-bit I/Os with through-silicon-via (TSV) distributed in 16 memory cores. Five-stage pipelined architecture in the compact DRAM core was developed to reduce the operation cycle of the data-bus to 2 ns. A low-noise early-bar-write scheme for an 8-ns cycle array operation and 16-Gbit/s I/O circuits on TSV were also developed. The proposed DRAM architecture greatly improves power efficiency. TSV scheme reduces the parasitic capacitance of the interconnects between the DRAM and CPU, and multi-core architecture reduces the length of the data bus on the DRAM. A 1-Gbit DRAM was designed based on the 45-nm stand-alone DRAM process. Chip size is 51.6 mm2 assuming 4F2 memory cells, and the density is about 5 times higher than that of embedded DRAM. Circuit simulations confirmed the 2-ns operation of the data bus, 8-ns operation of the memory array, and 16-Gbit/s operation of I/O circuits. Power consumption is 19.5 W, providing power efficiency of 51.3 Gbyte/s/W, which is an order of magnitude higher than that of conventional DRAMs.