SEKIGUCHI, T., ONO, K., KOTABE, A., & YANAGAWA, Y. (2011, Januar 1). 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. 46(4). New York, NY: Institute of Electrical and Electronics Engineers, 2011. Abgerufen von http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048

SEKIGUCHI, Tomonori, ONO, Kazuo, KOTABE, Akira und YANAGAWA, Yoshimitsu, 2011. 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. In: [online]. New York, NY: Institute of Electrical and Electronics Engineers, 2011. 1 Januar 2011. Available from: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048

SEKIGUCHI, T., K. ONO, A. KOTABE, und Y. YANAGAWA. 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. Nr. 4, New York, NY: Institute of Electrical and Electronics Engineers, 2011., 2011, http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048.

SEKIGUCHI, T., ONO, K., KOTABE, A. und YANAGAWA, Y. (2011), „1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing“, in , Bd. 46, New York, NY: Institute of Electrical and Electronics Engineers, 2011., verfügbar unter: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048.