SEKIGUCHI, T., ONO, K., KOTABE, A., & YANAGAWA, Y. (2011, January 1). 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. 46(4). New York, NY: Institute of Electrical and Electronics Engineers, 2011. Retrieved from http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048
ISO-690 (author-date, English)SEKIGUCHI, Tomonori, ONO, Kazuo, KOTABE, Akira and YANAGAWA, Yoshimitsu, 2011. 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. In: [online]. New York, NY: Institute of Electrical and Electronics Engineers, 2011. 1 January 2011. Available from: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048
Modern Language Association 9th editionSEKIGUCHI, T., K. ONO, A. KOTABE, and Y. YANAGAWA. 1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. no. 4, New York, NY: Institute of Electrical and Electronics Engineers, 2011., 2011, http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048.
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SEKIGUCHI, T., ONO, K., KOTABE, A. and YANAGAWA, Y. (2011), “1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing”, in , Vol. 46, New York, NY: Institute of Electrical and Electronics Engineers, 2011., available at: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=24154048.