Result: 100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2 Niobium Process

Title:
100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2 Niobium Process
Authors:
TANAKA, Masamitsu, AKAIKE, Hiroyuki, FUJIMAKI, Akira, YAMANASHI, Yuki, YOSHIKAWA, Nobuyuki, NAGASAWA, Shuichi, TAKAGI, Kazuyoshi, TAKAGI, Naofumi
Source:
The 2010 Applied Superconductivity Conference, Washington, DC, August 1-6, 2010IEEE transactions on applied superconductivity. 21(3):792-796
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2011.
Publication Year:
2011
Physical Description:
print, 9 ref 1
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Electrical engineering, Electrotechnique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs supraconducteurs, Superconducting devices, Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits électroniques, Electronic circuits, Circuits numériques, Digital circuits, Electrotechnique. Electroenergetique, Electrical engineering. Electrical power engineering, Matériel électrique divers, Various equipment and components, Electroaimants, Electromagnets, Circuit arithmétique, Arithmetic circuit, Circuito aritmético, Circuit logique, Logic circuit, Circuito lógico, Arithmétique numérique, Digital arithmetic, Basse fréquence, Low frequency, Baja frecuencia, Bobine inductance, Inductor, Bobina inductancia, Boucle réaction, Feedback, Retroalimentación, Circuit NON OU, NOR circuit, Circuito NI, Circuit additionneur, Summing circuits, Circuit intégré supraconducteur, Superconducting integrated circuits, Circuit intégré, Integrated circuit, Circuito integrado, Circuit logique supraconducteur, Superconducting logic circuits, Conception circuit, Circuit design, Diseño circuito, Densité courant critique, Critical current density, Densidad corriente crítica, Evaluation performance, Performance evaluation, Evaluación prestación, Grande vitesse, High speed, Gran velocidad, Horloge, Clock, Reloj, Information quantique, Quantum information, Información cuántica, Jonction Josephson, Josephson junction, Unión Josephson, Logique quantique, Quantum logic, Lógica cuántica, Régime fonctionnement, Operating rate, Régimen funcionamiento, Résistance série, Series resistance, Resistencia en serie, Tension polarisation, Bias voltage, Voltage polarización, single-flux-quantum logic, superconducting integrated circuits
Time:
0367
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Nagoya University, Nagoya 464-8603, Japan
Yokohama National University, Yokohama 240-8501, Japan
Superconductivity Research Laboratory, ISTEC, Tsukuba 305-8501, Japan
Kyoto University, Kyoto 606-8501, Japan
ISSN:
1051-8223
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=24276090
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electrical engineering. Electroenergetics

Electronics
Accession Number:
edscal.24276090
Database:
PASCAL Archive

Further Information

This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2 and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.